Certain non-volatile memory devices may operate by trapping charges in a dielectric interface to adjust the threshold voltage of a transistor and thus program the desired digital value of the transistor. One method of trapping charges is found in nonvolatile read-only memory (NROM) devices that use a silicon nitride layer between a tunnel oxide layer and a blocking oxide layer to trap charges.
NROM devices may be used to replace floating gate nonvolatile memory, such as flash memory, since the equivalent oxide thickness (EOT) may be reduced, as compared to the two separate insulator layers sometimes used in flash devices (e.g., one below the floating gate electrode and one between the floating gate and the control gate electrode). A lower EOT may result in faster devices having increased reliability, due to less reliance on physically thin insulator layers.
For example, in a floating gate memory each one of the two surfaces of each insulator layer may be in contact with a conductive surface since each insulator layer may be located between conductive electrodes such as the substrate, the floating gate, and the control gate. Thus, a defect in either insulator layer may cause a device failure in a floating gate device. As a matter of contrast, defects may have less effect in an NROM device since the insulators can be in contact with each other, such as the nitride insulator between the tunnel and blocking insulators.
A potential issue with the use of a deposited nitride layer between the tunnel insulator and the blocking insulator is that the growth of a nitride layer on other insulator layers typically exhibits what is known as an incubation period, which may vary from place to place on the insulator. This may result in a non-uniform thickness nitride charge trapping layer, sometimes providing an increased EOT.
Another potential issue with the use of a nitride layer between two oxide layers (e.g., ONO) is that the physical thickness of the nitride layer can result in trapped charges that are at different distances from the semiconductor channel region and thus have slightly different effects on the channel. Threshold voltages may thus have a wider distribution from one device to another, or from one programming cycle to another, as the physical thickness of the nitride layer may be proportional to the threshold voltage variation range.
Yet another issue with nonvolatile memory devices using a nitride layer between a tunnel insulator and a blocking insulator is that the injected electrons may pass through the tunnel insulator as desired but not be trapped in the nitride layer and pass through the blocking insulator to be lost to the gate electrode. This charge loss situation may result in increased programming, or “write” times, and potentially increased write voltages. Thus, there is a need for improved structures and methods with respect to the manufacture of non-volatile or persistent memory devices, such as NROM devices.